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ImSTDP: Implicit Timing On-Chip STDP Learning
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DOI：10.1109/TCSI.2024.3450958.png)
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摘要
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Spike-Timing-Dependent Plasticity (STDP) is a biological-plausible learning mechanism widely adopted for building Spiking Neural Networks (SNNs). It determines plasticity polarity and synapse strength change according to the timing difference between pre-and postsynaptic spikes. The learning curves of STDP differ in temporal window size, magnitude and polarity across different synapse types and brain regions and even within a cell, in different dendritic compartments. To accelerate on-chip STDP learning, various implementations have been proposed. However, they either introduce significant latency due to costly counter-based time difference calculation and substantial area cost due to the implementation of weight change LUTs, or lose biologically-plausible timing information due to oversimplification. For low-cost and efficient on-chip learning, a high-throughput Implicit-timing STDP (ImSTDP) with optimized SR depth and a low-cost register-based Implicit-Timing Look-up (ITL) are proposed. ASIC implementation in 22 nm technology demonstrates that ImSTDP can achieve up to 2 $\times$ throughput improvement and 3.61 $\times$ power efficiency improvement at 27% less area cost compared to the cutting-edge counter-LUT on-chip STDP learning solution.
Keyword:
Timing
System-on-chip
Synapses
Neurons
Costs
Table lookup
Biology
Neuromorphic computing
spiking neural networks
spike-timing-dependent plasticity
on-chip learning
期刊
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5.2
论文数:
9.7K
被引数:
2.2W
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