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In-Memory Multibit Multiplication Based on Bitline Shifting
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AI
DOI：10.1109/TCSII.2021.3099798.png)
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摘要
En 中文
Artificial intelligence algorithms entail an enormous number of multiplication operations. If these operations are implemented within a static random-access memory array, the considerable data migration between the memory and processor can be avoided; hence, a substantial amount of energy and time can be saved. Therefore, in-memory multibit multiplication is an important method for improving energy efficiency. However, the results of in-memory calculations are expressed in the form of bitline voltage. For an increase in the number of operation bits, the voltage representing the least-significant bit (LSB) of the operation result must decrease. To overcome this problem, we propose a strategy that decomposes multibit multiplication into combinations of binary operations based on bitline shifting. The voltage differences can be stored at different corresponding capacitances instead of at one point. Therefore, the LSB voltage difference remains high when the number of supported bits increases; for example, when 16 4 x 3 bits are calculated simultaneously, the LSB of the multiplication-accumulation result can reach 10 mV. The proposed in-memory multibit multiplication is achieved at similar to 282 MHz with 25.9 TOPS/W energy consumption.
Keyword:
Bitline shifting
in-memory computing
multibit multiplication
期刊
I
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4.9
论文数:
8.8K
被引数:
2.5W
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