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Industrial reliability testing of transistor gate dielectrics
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DOI：10.1038/s41928-026-01644-x.png)
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Abstract
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Transistors are currently undergoing a reinvention due to the stagnation of lateral scaling, the advance of three-dimensional stacking and the introduction of novel nanomaterials such as two-dimensional materials. A critical issue in the development of novel transistors is gate dielectric reliability, as the dielectric needs to withstand high electrical fields and block charge transport to guarantee correct device functioning. However, while attempts have been made in the academic literature to benchmark the figures of merit of transistors, the methodologies proposed for the study of gate dielectrics typically do not match industrial requirements. Here we explore how to evaluate the reliability of a dielectric material in an industry-relevant manner. We examine how industry benchmarks the performance of gate dielectrics in silicon transistors, how to collect and analyse gate dielectric reliability data to extract meaningful and industry-relevant conclusions, and how to apply this to two-dimensional transistors using gate dielectrics such as CaF2 and hexagonal boron nitride. We provide, in particular, a data processing protocol to extract lifetime-specific maximum allowed use voltage from ramped voltage stress, and provide an Excel file as a simple tool to carry out this extraction. This Perspective examines how industry benchmarks the performance of gate dielectrics in silicon transistors, how to collect and analyse gate dielectric reliability data to extract meaningful and industry-relevant conclusions, and how to apply this to two-dimensional transistors.
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