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Iterative decoder architectures

delete2003-08-01
delete48
PRE
AI
B
Borivoje Nikolić
A
Anantharam, V
DOI：10.1109/MCOM.2003.1222729delete
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Abstract

Abstract

En 中文
Implementation constraints on iterative decoders applying message-passing. algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Turbo codes and low-density parity check codes, in particular, are evaluated in terms of their suitability for VLSI implementation in addition to their bit error rate performance as a function of signal-to-noise ratio. It is necessary to, consider efficient realizations of iterative decoders when area, power, and throughput of the decoding implementation are constrained by practical design issues of communications receivers.
Keywords:
PARITY-CHECK CODES
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Journal

IEEE Communications Magazine cover
IEEE Communications Magazine
IF:
8.2
Papers:
6.9K
Citations:
2.2W

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