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Level-Based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication
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DOI：10.1109/TPDS.2022.3223512.png)
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The multiplication of a sparse matrix with a dense vector (SpMV) is a key component in many numerical schemes and its performance is known to be severely limited by main memory access. Several numerical schemes require the multiplication of a sparse matrix polynomial with a dense vector which is typically implemented as a sequence of SpMVs. This results in low performance and ignores the potential to increase the arithmetic intensity by reusing the matrix data from cache. In this work we use the recursive algebraic coloring engine (RACE) to enable blocking of sparse matrix data across the polynomial computations. In the graph representing the sparse matrix we form levels using a breadth-first search. Locality relations of these levels are then used to improve spatial and temporal locality when accessing the matrix data and to implement an efficient multithreaded parallelization. Our approach is independent of the matrix structure and avoids shortcomings of existing blocking strategies in terms of hardware efficiency and parallelization overhead. We quantify the quality of our implementation using performance modelling and demonstrate speedups of up to 3x and 5x compared to an optimal SpMV-based baseline on a single multicore chip of recent Intel and AMD architectures. Various numerical schemes like $s$s-step Krylov solvers, polynomial preconditioners and power clustering algorithms will benefit from our development.
Keyword:
Algorithm design and analysis
computer architecture
graph algorithms
kernel optimization
memory hierarchies
performance evaluation
sparse matrices
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6
论文数:
5.2K
被引数:
1.1W
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