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Libra: An Automatic Design Methodology for CMOS Complex Gates
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DOI：10.1109/TCSII.2018.2866231.png)
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Recent papers have shown that the circuit design based on complex gates generated under demand became a valuable alternative to surpass the well-known standard cell approach, especially for critical parts of digital systems, which contains a high restrictive specification level. Through this strategy, it is possible to minimize the number of transistors, potentially optimizing the circuit in electrical and geometrical domains. On the other hand, this paradigm is limited considering the increasing complexity of digital systems and its dependence on the circuit designer. In this scenario, we propose the Libra methodology, an automatic approach for the design of CMOS complex logic gates. Libra is based on a transistor network generation paradigm capable to deliver solutions with diversified topologies. Furthermore, it has a flexible gate sizing methodology and a layout generation process under demand, which includes automatic placement, routing, and compaction. Besides that, it implements on-the-fly validation, verification and test routines. This way, it is possible to compare our tool with the widely used method for complex gate design. Experiments have shown that Libra can deliver optimized cells in terms of area and delay relative to the solutions obtained from the usual Boolean factoring paradigm.
Keyword:
Libra
digital circuit
complex gate
logic gate
SCCG
transistor network
layout
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