Lossless Differential Table Compression for Hardware Function Evaluation

Maxime Christ

doi:10.1109/TCSII.2021.3131405

Lossless Differential Table Compression for Hardware Function Evaluation

2022-03-01

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DOI：10.1109/TCSII.2021.3131405

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Hsiao et al. recently introduced, in the context of multipartite table methods, a lossless compression technique that replaces a table of numerical values with two smaller tables and one addition. The present work shows that this technique has many more applications than originally published, and that in many of these applications the addition is for free in practice. It also improves this technique and the resulting architecture by exposing a wider implementation space, and an exhaustive but fast algorithm exploring this space. These contributions are implemented in the open-source FloPoCo core generator and evaluated on FPGA and ASIC, reducing area up to a factor 2.

Keywords:

Costs

Table lookup

Field programmable gate arrays

Space exploration

Hardware

Indexes

Generators

Table of numerical values

hardware function evaluation

compression

computer arithmetic

ASIC

FPGA

Lossless Differential Table Compression for Hardware Function Evaluation

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