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Low energy asynchronous architectures
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DOI：10.1109/ISCAS.2005.1465816.png)
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Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and delay tolerance is the principal design goal, and where performance is not a critical requirement. Three existing adder circuits are studied - two dynamic and one based on pass-transistor logic. All adders combine dual-rail and bundled-data circuits. The circuits are simulated at a wide supply-voltage range, down to their minimal operating point. Leakage energy (at 0.18 mu m) is found negligible. Transistor count is found to be an unreliable predictor of energy dissipation. A set of the energy minimization rules is defined and two novel adders are proposed, based on these rules - a dynamic circuit and a pass-transistor logic adder. The new adders consume less energy and achieve better performance, confirming the proposed concepts.
Keyword:
low energy
adder
asynchronous logic
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