Low power H.264 deblocking filter hardware implementations

Mustafa Parlak

doi:10.1109/TCE.2008.4560164

2008-05-01

PRE

Mustafa Parlak *

Hamzaoglu, Ilker

DOI：10.1109/TCE.2008.4560164

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摘要

En 中文

In this paper, we present two efficient and low power H.264 deblocking filter (DBF) hardware implementations that can be used as part of an H.264 video encoder or decoder for portable applications. The first implementation (DBFI_4x4) starts filtering the available edges as soon as a new 4x4 block is ready by using a novel edge filtering order to overlap the execution of DBF module with other modules in the H.264 encoder/decoder. Overlapping the execution of DBF hardware with the execution of the other modules in the H.264 encoder/decoder improves the performance of the H.264 encoder/decoder. The second implementation (DBF_16x16) starts filtering the available edges after a new 16x16 macroblock is ready. Both DBF hardware architectures are implemented in Verilog HDL and both implementations are synthesized to 0.18 mu m UMC standard cell library. Both DBF implementations can work at 200 MHz and they can process 30 VGA (640x480) frames per second DBF_4x4 and DBF_16x16 hardware implementations, excluding on-chip memories, are synthesized to 7.4 K and 5.3 K gates respectively. These gate counts are the lowest among the H.264 DBF hardware implementations presented in the literature. Our hardware implementations are more cost effective solutions for portable applications. DBF_16x16 has 36% less power consumption than DBF_4x4 on a Xilinx Virtex II FPGA on an Arm Versatile PB926EJ-S development board Therefore, DBF_4x4 hardware can be used in an H.264 encoder or decoder for which the performance is more important, whereas DBF_16x16 hardware can be used in an H.264 encoder or decoder for which the power consumption is more important.

Keyword:

H.264

video coding

deblocking filter

hardware implementation

FPGA

low power