Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process

doi:10.1109/TCSII.2014.2319676

2014-06-01

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DOI：10.1109/TCSII.2014.2319676

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摘要

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This brief presents a multicore embedded processor with reconfigurable same-instruction multiple process (RSIMP) architecture design to reduce the power consumption of instruction memory (IM), thus reducing the total power of the processor. RSIMP is applied to the scenario in which several cores (each representing a coarse-grained process) execute a highly identical instruction sequence in parallel. They are then reconfigured to master-slave mode in which only the master core fetches instructions and distributes the instructions to the slave core(s), whereas the IM of slave cores are shut down to save power. Experimental results show 13.8% and 21.9% of system power reduction with negligible hardware overhead and performance loss in 2Core and 4Core configurations, respectively, for the benchmarks selected from the long-term evolution (LTE) multiple-input-multiple-output (MIMO) system, the Reed-Solomon (RS) decoder, the H.264/AVC codec, and AES encryption/decryption, compared with the baseline platform.

Keyword:

Instruction memory (IM)

low power

multicore processor

reconfigurable same-instruction multiple process (RSIMP)