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Low-Power Ternary Multiplication Using Approximate Computing
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DOI：10.1109/TCSII.2021.3068971.png)
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摘要
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We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and 2x2 ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient 6x6 approximate ternary multipliers. The energy benefit of the proposed 6x6 approximate ternary multipliers have been verified using HSPICE simulation. The proposed approximate design shows 82.8% power-delay product with 41.8% mean absolute percentage error improvement over the previous approximate multiplier-based design. Image processing applications are conducted using the proposed approximate designs to confirm that the accuracy of ternary multiplication is satisfied the user's requirement.
Keyword:
Multi-valued Logic
ternary Logic Circuits
CNTFET
ternary multiplier
approximate computing
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