Low resource FPGA implementation based efficient image edge detector architecture

Sidharth Kashyap

doi:10.1007/s11042-023-16472-w

2023-08-22

PRE

Sidharth Kashyap

Ashish Kumar Bhandari *

Pushpa Giri

DOI：10.1007/s11042-023-16472-w

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摘要

En 中文

This paper proposes a resource-efficient architecture of Sobel edge detector, Prewitt edge detector, Roberts edge detector and Laplacian edge detector on the field programmable gate arrays (FPGAs). The proposed architecture is less complex as well as uses lower resources compared to conventional architecture. The rank properties of the convolution kernel followed by pipelining and concurrent output methods have been implemented to reduce the arithmetic operation without compromising the output conformance. In addition, buffering scheme has also been used to reduce Block RAM (BRAM) consumption and bandwidth between external memory and FPGA. All four edge detection techniques have been depicted and compared at various threshold values. The power and resource consumption followed by execution time (software and hardware) have been estimated and compared of various method at clock frequency 100 MHz for 512x512 image resolution. The Sobel edge detector with the proposed architecture shows overall better performance compared to other edge detection techniques. Furthermore, a number of arithmetic operations, and resources using 8-bit architecture as well as 10-bit architecture of proposed Sobel algorithm have been investigated and compared with existing Sobel algorithm. The proposed architecture is implemented on the Xilinx Zynq (TM)-7000 FPGA board. The proposed architecture method paves the way to process 325 frames per second and power consumption is 0.107 W.

Keyword:

Edge detector

Low resource consumption

Sobel edge detector

Roberts edge detector

Laplacian edge detector and FPGA