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Low-temperature dopant activation technology using elevated Ge-S/D structure
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DOI：10.1016/j.apsusc.2003.08.094.png)
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摘要
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Dopant activation annealing of an elevated Ge-S/D structure formed on Si was investigated for application in advanced CMOSFET fabrication. Due to the low melting point of Ge, dopant activation was observed below 600 degreesC. However, the low temperature annealing process resulted in high reverse-bias p-n junction leakage. A thermal process budget of 900 degreesC, 60 s was found to be the minimum necessary for achieving low junction leakage. The location of the junction after the 900 degreesC annealing can be as shallow as similar to20 run beneath the original Si interface for both p+/n and n+/p diodes. (C) 2003 Published by Elsevier B.V.
Keyword:
shallow junction
elevated S/D
Ge
CMOS
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期刊
IF:
6.9
论文数:
6.2W
被引数:
19.4W
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