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Machine Learning Hardware Design for Efficiency, Flexibility, and Scalability [Feature]
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DOI：10.1109/MCAS.2023.3302390.png)
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摘要
En 中文
The widespread use of deep neural networks (DNNs) and DNN-based machine learning (ML) methods justifies DNN computation as a workload class itself. Beginning with a brief review of DNN workloads and computation, we provide an overview of single instruction multiple data (SIMD) and systolic array architectures. These two basic architectures support the kernel operations for DNN computation, and they form the core of many flexible DNN accelerators. To enable a higher performance and efficiency, sparse DNN hardware can be designed to gain from data sparsity. We present common approaches from compressed storage to processing sparse data to reduce memory and bandwidth usage and improve energy efficiency and performance. To accommodate the fast evolution of new models of larger size and higher complexity, modular chiplet integration can be a promising path to meet the growing needs. We show recent work on homogeneous tiling and heterogeneous integration to scale up and scale out hardware to support larger models of more complex functions.
Keyword:
Surveys
Scalability
Multichip modules
Artificial neural networks
Machine learning
Bandwidth
Tutorials
Design engineering
Hardware design languages
ML hardware
DNN accelerator
sparse DNN architecture
DNN chiplet
heterogeneous integration
期刊
IF:
3.5
论文数:
525
被引数:
1.3K
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