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Maximum Likelihood Estimation-Based SAR ADC
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DOI：10.1109/TCSII.2018.2886260.png)
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A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with maximum likelihood estimation (MLE) is presented in this brief. After SAR quantization is finished, the comparator is fired 18 times and the outputs are sent to the estimator for calculation of the residue voltage. The estimator output is subtracted from the SAR output to form the overall output. MLE improves the ADC SNR by more than 8 dB without the need for prior knowledge of SAR noise distribution. A prototype ADC in 65 nm process achieves an average SNR of 64.5 dB at sampling frequency of 1.28 MHz and power supply of 1 V while consuming 5.6 fJ/conversion-step. The estimation accuracy is consistent across voltage and temperature ranges.
Keyword:
Successive approximation register (SAR)
analog-to-digital converter (ADC)
maximum likelihood estimation
stochastic ADC
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