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Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes
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DOI：10.1109/TCSII.2020.3011220.png)
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Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.
Keyword:
Decoding
Manganese
Reliability
Complexity theory
Memory management
Circuits and systems
Parity check codes
Message compression
error-correction
layered decoder
nonbinary low-density parity-check (NB-LDPC)
trellis min-max (TMM)
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