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Mitigating Process Variability for Non-Volatile Cache Resilience and Yield
DOI:10.1109/TETC.2018.2799005.png)
Abstract
En 中文
While inclusion of emerging technology-based Non-Volatile Memory (NVM) devices in on-chip memory subsystems offers excellent potential for energy savings and scalability, their sensing vulnerability creates Process Variation (PV) challenges. This paper presents a circuit-architecture cross-layer solution to realize a radically-different approach to leveraging as-built variations via specific Sense Amplifier (SA) design and use. This novel approach, referred to as a Self-Organized Sub-bank (SOS) design, assigns the preferred SA to each Sub-Bank (SB) based on a PV assessment, resulting in energy consumption reduction and increased read access reliability. To improve the PV immunity of SAs, two reliable and power efficient SAs, called the Merged SA (MSA) and the Adaptive SA (ASA) are introduced herein for use in the SOS scheme. Furthermore, we propose a dynamic PV and energy-aware cache block migration policy that utilizes mixed SRAM and STT-MRAM banks in Last Level Cache (LLC) to maximize the SOS bandwidth. Our experimental results indicate that SOS can alleviate the sensing vulnerability by 89 percent on average, which significantly reduces the risk of application contamination by fault propagation. Furthermore, in the light of the proposed block migration policy, write performance is improved by 12.4 percent on average compared to the STT-MRAM-only design.
Keywords:
Magnetic tunneling
Sensors
Reliability engineering
Random access memory
Nonvolatile memory
Energy consumption
Magnetic tunneling junction (MTJ)
spin-transfer torque storage elements
STT-MRAM
self-referencing MTJ
reliability
process variation
read
write reliability
sub-banking
last level cache (LLC)
sense amplifier (SA) design
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