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ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation
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DOI：10.1109/TCSI.2021.3133931.png)
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摘要
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In this article, we propose a multiplierless piecewise linear (PWL) approximation computation (ML-PLAC) method for nonlinear unary functions. ML-PLAC seeks the minimum number of segments with the predefined fractional bit width and number of adders to satisfy the restriction on the maximum absolute error (MAE). Compared with the previous universal PWL approximation method, multiplication operations in the segmentor are replaced by a simulation of shift-and-add operations by reducing the fractional bit width of the slope of linear functions. Various numbers of segments are obtained by different predefined numbers of adders to balance the two numbers. In addition, adders are used to replace the multiplier in hardware architecture. The synthesized results prove that ML-PLAC has increased performance without any compromises. Compared with state-of-the-art methods, ML-PLAC saves 58.82% area, 38.16% delay, 60.31% power and 6.10% MAE when computing logarithmic functions; 51.51% area, 46.49% delay, and 46.95% power while maintaining the comparable MAE when computing antilogarithmic functions; 55.21% area, 25% delay, 61.21% power, and 37.30% MAE when computing hyperbolic tangent functions; 82.47% area, 60% delay, 77.51% power and 12.74% MAE when computing sigmoid functions; and 46.43% area, 31.43% delay, and 61.16% power while maintaining the same MAE when computing softsign functions.
Keyword:
Hardware
Delays
Adders
Computer architecture
Table lookup
Approximation methods
Speech recognition
Piecewise linear (PWL) approximation method
maximum absolute error (MAE)
logarithmic function
antilogarithmic function
hyperbolic tangent function
sigmoid function
softsign function
期刊
IF:
5.2
论文数:
9.8K
被引数:
2.2W
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引用论文
Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations
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