Models for control unit synchronization on shared control architectures

Abu-Ghazaleh, NB

doi:10.1006/jpdc.1998.1468

Models for control unit synchronization on shared control architectures

1998-07-01

0

PRE

AI

DOI：10.1006/jpdc.1998.1468

原文链接

原文求助

摘要

En 中文

Shared control is an architecture model that extends the SIMD model to support control parallelism. Under shared control, each processing element (PE) supports a local instruction stream and control for each PE is received by synchronizing with a shared control unit corresponding to the PE's current instruction. Because the control is shared and not supplied on demand, the control units must be tightly synchronized to allow the PEs to select among them. This synchronization is accomplished by defining a fundamental cycle length for the control units-allowing PEs to safely switch to a new control unit at the fundamental cycle edge. In a naive implementation, the fundamental cycle length is governed by the longest instruction length; other control units are padded with idle cycles to that length. Since the longest instruction cost is suffered by each instruction, the performance of the system in the presence of long instructions deteriorates. This paper presents and evaluates alternative models for synchronization that minimize the effect of long instructions on the performance. The implementation of these solutions is discussed and the improvement in performance is characterized. (C) 1998 Academic Press, Inc.

Keyword:

SIMD

Models for control unit synchronization on shared control architectures

摘要

期刊

机构

引用论文