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Motion Estimation for Video Coding Efficient Algorithms and Architectures Introduction
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DOI：10.1007/978-3-319-14376-7_1.png)
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Abstract
En 中文
Video data consist of a time sequence of image frames, and there exists a significant redundancy in temporal domain. One of the important aims of video compression is removal of the temporal redundancy in an efficient way. Motion Estimation (ME), which tries to remove the temporal redundancy by finding the best matching block in a reference frame for each block in the present frame, is the principal component of a video encoding system. Of all the components of a video encoder, the ME module consumes the lion's share of overall power. A very simple arithmetic computation is required for ME. However, frequent memory access associated with ME affects the overall speed of operation and the power consumption. The present work has therefore focused on design and development of several fast ME architectures characterized by high processing speed, low power, and low area making them suitable for portable video application devices that are typically operated by battery power and involve real time operation. VLSI architecture has been developed for Fast Three Step Search (FTSS) algorithm that is used in video conferencing applications. An intelligent data arrangement has been used in this design to reduce the power consumption and to achieve a high speed of operation. Parallel VLSI architectures for Successive Elimination algorithm (SEA) have also been developed. The architecture proposed for SEA requires nearly 60 % less time with same power requirement and accuracy, but somewhat more area while being compared to an architecture meant for realizing full search algorithm. Moreover, the present work has conceived fast ME by combining One Bit Transformation (1BT) for fixed block size and single reference frame. Fast 1BT based ME architectures for variable block size and single reference frame and multiple reference frames have also been developed. The scope of the present work also includes fast ME algorithms based on the pixel truncation. An appropriate architecture has also been developed for implementing the proposed ME algorithm. In the present work, all the proposed architectures have been synthesized and analyzed for power and maximum operating frequencies in FPGA as well as ASIC platforms. Nowadays, the consumer looks out for the best possible video quality regardless of his/her location and degree of network support. To realize this however, the transmitted video must match the receiver's characteristics such as the required bit rate, resolution and frame rate, thus aiming to provide the best quality subject to the limitations of the receiver and the network. Scalable video coding provides an appropriate solution to this type of problem. In recent years, wavelet-based image and video coding systems that utilize a wide range of spatial, temporal and SNR scalability with state-of-the-art coding performance have been developed. An introduction to scalable video coding based in-band motion compensated temporal filtering (IB-MCTF) has been provided towards the end of this book.
Keywords:
Video compression
Fast three step search
Successive elimination
One-bit transformation
Pixel truncation
Parallel VLSI architecture
Scalable video coding
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