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Multi-Function Scan Circuit for Assisting the Parallel Computational Map Pattern
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DOI：10.59277/ROMJIST.2024.1.01.png)
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摘要
En 中文
Some parallel computing patterns can be accelerated using appropriate networks of simple circuits. We propose a solution, based on the Benes-Waksman permutation network, which is adapted to efficiently accelerate not only permutation, but some of the most used parallel computational patterns such as: pack, prefix operations and reductions. The structural context considered for deploying our circuit is the map parallel pattern represented by an array of computational elements. The developed network receives a vector from the map array and outputs a vector for functions such as permute, pack, prefix sum (thus closing a first global loop over the map array of cells). For reduction functions (add, min, max) the network returns a scalar (thus closing a second global loop over the map array). With these improvements, this network adds circuit support for frequently used functions, in addition to map-type functions performed in the array of computing elements. While for reduction functions the frame of the permutation network can be easily adapted, for prefix functions and for the pack function new forms of implementation are proposed. The cells of the Benes-Waksman network are redesigned to support the additional functionality. Some applications are then presented to emphasize the utility of our design.
Keyword:
Benes network
General-Purpose Accelerator
Multi-Function Permutation circuit
Scan Circuit
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