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Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing
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DOI：10.1109/JETCAS.2023.3243434.png)
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摘要
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The widely used Von Neumann architecture must move data between memory and the computation unit when performing operations, which causes a performance bottleneck. In-memory computing is an effective way to reduce the bottleneck; therefore, we design an in-memory Boolean computing architecture based on static random access memory (SRAM). We also propose a new multi-logic sense amplifier (MLSA) design, an improvement over conventional sense amplifiers that only perform a single logical operation, either NOR/OR or NAND/AND. Our design can generate multiple logical outputs, including OR/NOR, AND/NAND, and XOR/XNOR, with a lower compute delay, lower power consumption, and less transistor count. In the experimental results, the proposed MLSA design reduces the NAND, AND, and XNOR delay by 62%, 39%, and 30%, and it also decreases the static power consumption by 40% and dynamic power consumption in computing operations by 22% compared to the conventional sensing method.
Keyword:
Computer architecture
Discharges (electric)
Transistors
Voltage
In-memory computing
Delays
Sensors
Static random access memory (SRAM)
in-memory computing
sense amplifier (SA)
期刊
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3.8
论文数:
1.4K
被引数:
2.8K
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