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Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal
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DOI：10.1109/TCSII.2018.2880921.png)
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摘要
En 中文
This brief presents novel circuits for calculating the bit reversal on parallel data. The circuits consist of delays/memories and multiplexers, and have the advantage that they requires the minimum number of multiplexers among circuits for parallel bit reversal so far, as well as a small total memory.
Keyword:
Bit reversal
FFT
pipelined architecture
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期刊
I
IF:
4.9
论文数:
8.8K
被引数:
2.5W
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