Multiprocessor shared memory access and rewards

doi:10.1016/S0016-0032(96)00142-1

Multiprocessor shared memory access and rewards

1998-05-01

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DOI：10.1016/S0016-0032(96)00142-1

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Computer architecture and software have evolved largely independently of mathematical models for computers as physical systems. Most bus arbitration policies are independent of the algorithm being executed on the multiprocessing architecture. While this may be adequate for platforms for which utilization is much smaller than capacity, high-performance applications require maximum utilization of resources: Communications technologies such as Asynchronous Transfer Merle (ATM) have demonstrated the usefulness of arbitration schemes that are application dependent. This paper introduces the application of a Markov analysis based upon rewards to bus arbitration in shared memory architectures. A two-processor example is developed which relates system gain to algorithm. Generalization is provided so the formulation may be extended to N processors. (C) 1997 The Franklin Institute. Published by Elsevier Science Ltd.

Multiprocessor shared memory access and rewards

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