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NeuralTimer: Configuration-Based Neural Network Approach to Hardware Timer-Based Applications
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DOI：10.1109/ACCESS.2026.3656830.png)
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摘要
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Hardware timers are fundamental components in time-critical embedded systems, where precise and deterministic timing control is essential for operations such as real-time signal processing, task scheduling, sensor data acquisition, and synchronization. Even small timing inaccuracies can lead to degraded performance or system malfunction. This paper presents a novel NeuralTimer architecture that replaces conventional register-based timer logic with a compact neural network implemented on the Xilinx Zybo Z7-20 FPGA platform. The design operates at the board’s native 125 MHz clock frequency and realizes an 8-bit threshold-based timing mechanism capable of adaptive and high-level timing control. Unlike traditional timers that require hardware-dependent configuration through prescalers and registers, the proposed approach enables reconfiguration simply by updating the neural network weights. Experimental validation demonstrates stable real-time performance confirming that neural-network-driven timers can serve as flexible, resource-efficient, and reconfigurable control primitives for next-generation embedded systems.
Keyword:
Embedded systems
field-programmable gate array (FPGA)
hardware timer
neural network
期刊
IF:
3.6
论文数:
9.8W
被引数:
29.4W
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