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Neuromorphic Hardware Architecture Using the Neural Engineering Framework for Pattern Recognition
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DOI：10.1109/TBCAS.2017.2666883.png)
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摘要
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We present a hardware architecture that uses the neural engineering framework (NEF) to implement large-scale neural networks on field programmable gate arrays (FPGAs) for performing massively parallel real-time pattern recognition. NEF is a framework that is capable of synthesising large-scale cognitive systems from subnetworks and we have previously presented an FPGA implementation of the NEF that successfully performs non linear mathematical computations. That work was developed based on a compact digital neural core, which consists of 64 neurons that are instantiated by a single physical neuron using a time multiplexing approach. We have now scaled this approach up to build a pattern recognition system by combining identical neural cores together. As a proof of concept, we have developed a handwritten digit recognition system using the MNIST database and achieved a recognition rate of 96.55%. The system is implemented on a state-of-the-art FPGA and can process 5.12 million digits per second. The architecture and hardware optimisations presented offer high-speed and resource-efficient means for performing highspeed, neuromorphic, and massively parallel pattern recognition and classification tasks.
Keyword:
MNIST
neuromorphic engineering
neural engineering framework
pattern recognition
pseudo inverse
time-multiplexing
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