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Numerical function generators using LUT cascades
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DOI：10.1109/TC.2007.1033.png)
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This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA).
Keyword:
LUT cascades
numerical function generators (NFGs)
nonuniform segmentation
automatic synthesis
FPGA implementation
期刊
IF:
3.8
论文数:
5.3K
被引数:
9.8K
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