Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache

Faaiq Waqar

doi:10.1109/TC.2025.3625490

2025-10-24

PRE

Mohammadhosein Gholamrezaei

Kevin Skadron

Shimeng Yu

DOI：10.1109/TC.2025.3625490

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摘要

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末级缓存（LLC）是处理器片上与片外存储层级间的关键桥梁，其优化目标为高密度、高带宽和低操作能耗。迄今为止，高密度（HD）SRAM一直是传统的首选器件；然而，随着晶体管缩放放缓（如业界从5 nm到3 nm工艺中HD SRAM单元尺寸几乎不变），替代方案（如采用先进封装的3D堆叠，即混合键合）正被探索（如AMD的V-cache所示）。日益增长的数据需求需要超大规模片上缓存以减少昂贵的片外存储访问，推动器件技术探索走向单晶圆3D（M3D）集成，其中晶体管可在后端工艺（BEOL）的互连层级堆叠。M3D集成需要与低热预算（<400°C）兼容的制造技术。在前景广阔的BEOL器件候选中，非晶氧化物半导体（AOS）晶体管因其超低漏电（秒级）。本文考察了在优化BEOL兼容的AOS基2晶体管增益单元（2T-GC）用于LLC时的器件、电路及系统级权衡。开发了一种缓存早期探索工具NS-Cache，用于在先进7 nm和3 nm节点中建模缓存，并与Gem5模拟器集成，以系统性地评估与HD-SRAM、MRAM及1T1C eDRAM替代方案相比，新发现的密度/性能对LLC的影响。

Keyword:

Last-level cache

monolithic 3-D integration

gain cell

amorphous oxide semiconductors

persistent memory

期刊

IEEE Transactions on Computers

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3.8

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5.3K

被引数:

9.8K

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georgia institute of technology

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2.2K

论文数: 1.1K

被引数: 0

university of virginia

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4.4K

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