Optimization of Graphical Parameter Extraction Algorithm for Chip-Level CMP Prediction Model Based on Effective Planarization Length

Bowen Ren

doi:10.3390/mi15040549

Optimization of Graphical Parameter Extraction Algorithm for Chip-Level CMP Prediction Model Based on Effective Planarization Length

2024-04-19

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DOI：10.3390/mi15040549

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As a planarization technique, chemical mechanical polishing (CMP) continues to suffer from pattern effects that result in large variations in material thickness, which can influence circuit performance and yield. Therefore, tools for predicting post-CMP chip morphology based on the layout-dependent effect (LDE) have become increasingly critical and widely utilized for design verification and manufacturing development. In order to characterize the impact of patterns on polishing, such models often require the extraction of graphic parameters. However, existing extraction algorithms provide a limited description of the interaction effect between layout patterns. To address this problem, we calculate the average density as a density correction and innovatively use a one-dimensional line contact deformation profile as a weighting function. To verify our hypothesis, the density correction method is applied to a density step-height-based high-K metal gate-CMP prediction model. The surface prediction results before and after optimization are compared with the silicon data. The results show a reduction in mean squared error (MSE) of 40.1% and 35.2% in oxide and Al height predictions, respectively, compared with the preoptimization results, confirming that the optimization method can improve the prediction accuracy of the model.

Keyword:

die-scale CMP model

effective planarization length (EPL)

layout-dependent effects

density correction

HKMG

layout extraction

Optimization of Graphical Parameter Extraction Algorithm for Chip-Level CMP Prediction Model Based on Effective Planarization Length

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