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Optimized Pulse Patterns With Bounded Semiconductor Losses
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DOI：10.1109/TPEL.2023.3337329.png)
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Abstract
En 中文
This article proposes the computation of three-level optimized pulse patterns (OPPs) that achieve not only low harmonic load current distortions (load-friendly operation) but also low semiconductor losses (converter-friendly operation). To this end, the conduction and switching losses are modeled as a function of the OPP switching angles and the amplitude and phase of the converter current. By minimizing the current harmonics subject to an inequality constraint on the semiconductor losses, OPPs are derived that achieve minimal current distortions with a guaranteed upper bound on the semiconductor losses, thus ensuring the safe operation of the semiconductor switches within their thermal limits. Detailed numerical results for a medium-voltage system consisting of a neutral-point-clamped converter and an inductive load verify the benefits of this approach.
Keywords:
Switches
Harmonic analysis
Optimization
Voltage
Distortion
Harmonic distortion
Switching loss
Optimized pulse patterns (OPPs)
Pareto optimal solutions
semiconductor losses
three-level converters
Journal
IF:
6.5
Papers:
1.7W
Citations:
8.3W