Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format

doi:10.1109/TCSI.2023.3300657

Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format

2023-11-01

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DOI：10.1109/TCSI.2023.3300657

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In recent years, low-precision fixed-point computation has become a widely used technique for neural network inference on FPGAs. However, this approach has some limitations, as certain neural networks are difficult to quantify using fixed-point arithmetic, such as those involved in super-resolution scaling, image denoising, and other scenarios that lack sufficient conditions for fine-tuning. Furthermore, deploying a floating-point precision neural network directly on an FPGA would lead to significant hardware overhead and low computational efficiency. To address this issue, this paper proposes an FPGA-friendly floating-point data format that achieves the same storage density as int8 without sacrificing inference accuracy or requiring fine-tuning. Additionally, this paper presents an FPGA-based neural network accelerator that is compatible with the proposed format, utilizing DSP resources to increase the number of DSP cascading from 7 to 16, and solving the back-to-back accumulation issue of floating-point numbers. This design achieves comparable resource consumption and execution efficiency to those of 8-bit fixed-point accelerators. Experimental results demonstrate that the accelerator proposed in this study achieves the same accuracy as the native floating point on multiple neural networks without fine-tuning, and remains high computing performance. When deployed on the Xilinx ZU9P, the performance achieves 4.072 TFlops at 250 MHz, which outperforms the previous works, including the Xilinx official DPU.

Keyword:

Deep neural network

accelerator

low-precision floating point

field-programmable gate array (FPGA)

very large scale integration circuit (VLSI)

Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format

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