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Parallel CRC realization
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DOI：10.1109/TC.2003.1234528.png)
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摘要
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This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different from the degree of the polynomial generator. Last, we have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polyonomial is given.
Keyword:
parallel CRC
LFSR
error-detection
VLSI
FPGA
VHDL
digital logic
期刊
IF:
3.8
论文数:
5.4K
被引数:
9.8K
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