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Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs
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DOI：10.1109/TC.2014.2308202.png)
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SPICE is the de facto standard for circuit simulation. However, accurate SPICE simulations of today's sub-micron circuits can often take days or weeks on conventional processors. A SPICE simulation is an iterative process that consists of two phases per iteration: model evaluation followed by a matrix solution. The model evaluation phase has been found to be easily parallelizable, unlike the subsequent phase, which involves the solution of highly sparse and asymmetric matrices. In this paper, we present an FPGA implementation of a sparse matrix solver, geared towards matrices that arise in SPICE circuit simulations. Our approach combines static pivoting with symbolic analysis to compute an accurate task flow-graph which efficiently exploits parallelism at multiple granularities and sustains high floating-point data rates. We also present a quantitative comparison between the performance of our hardware prototype and state-of-the-art software packages running on a general-purpose PC. We report average speed-ups of 9.65x, 11.83x, and 17.21x against UMFPACK, KLU, and Kundert Sparse matrix packages, respectively.
Keyword:
Hardware acceleration
sparse matrices
SPICE
FPGA arithmetic
pipeline and parallel arithmetic and logic structures
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