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Performance evaluation of novel mid-insulation gate junctionless transistors at the device and circuit level
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Abstract
En 中文
This work proposes a novel gate-engineered Mid-Insulation Gate Junctionless Transistor (MiG-JLT) and presents a comparative performance evaluation against the conventional Symmetric Double Gate Junctionless Transistor (SDG-JLT). Under identical physical parameters, the proposed MiG-JLT demonstrates a nearly 35% enhancement in ON-state current, achieving an ON current of approximately 2.5 x 10(-5) A and an I-ON/I-OFF ratio of about 2.5 x 10(8). For a silicon body thickness of 10 nm, the device exhibits a peak transconductance of similar to 7 x 10(-5) S, and a drain conductance of similar to 1.3 x 10(-4) S at low drain bias, confirming its improved analog performance. The effects of doping concentration, surface potential distribution, and channel width are systematically analyzed. Circuit-level inverter analysis further demonstrates enhanced transfer and switching characteristics. Overall, the proposed MiG-JLT shows strong potential for high-performance nanoscale and SPICE-compatible device applications.
Keywords:
Mid-insulation gate
Junctionless transistor
Surface potential
Drain current
Transconductance
Journal
I
IF:
0.7
Papers:
50
Citations:
548
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Cited Papers