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Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation

delete2019-10-01
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M
Manuel Delgado‐Restituto
J
James Brian Romaine *
Á
Á. Rodríguez‐Vázquez
DOI:10.1109/TBCAS.2019.2931799delete
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摘要

摘要

En 中文
This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters, and adders. The processor, fabricated in a 0.18-$\mu$m CMOS process, only occupies 0.05mm$<^>2$ and consumes 15nW from a 0.5V supply voltage at a signal input rate of 1024S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.
Keyword:
Functional connectivity
low power CMOS VLSI
neural signal processing
phase synchronization
seizure detection
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期刊

IEEE Transactions on Circuits and Systems I-Regular Papers 封面图
IEEE Transactions on Circuits and Systems I-Regular Papers
IF:
5.2
论文数:
9.8K
被引数:
2.2W

机构

U
University of Sevilla
学者数:
1.9W
论文数: 1.7W
被引数: 15
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