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Power Distribution in TSV-Based 3-D Processor-Memory Stacks

delete2012-12-01
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S
Suhas M. Satheesh
E
Emre Salman *
DOI:10.1109/JETCAS.2012.2223553delete
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摘要

摘要

En 中文
Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a 3-D processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this paper. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a 3-D power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to the number of TSVs and decoupling capacitance.
Keyword:
Decoupling capacitance
embedded memory
IR drop
Ldi/dt noise
power delivery
power supply noise
processor-memory stacks
three-dimensional (3-D) integrated circuits
through silicon via (TSV)
via-first
via-middle
via-last
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期刊

IEEE Journal on Emerging and Selected Topics in Circuits and Systems 封面图
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
IF:
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论文数:
1.4K
被引数:
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state university of new york (suny) system
学者数:
6.5W
论文数: 5.8W
被引数: 65
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