Power efficient synchronous counter design

Raghava Katreepalli

doi:10.1016/j.compeleceng.2018.01.001

Power efficient synchronous counter design

2019-05-01

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R

Raghava Katreepalli *

T

Themistoklis Haniotakis

DOI：10.1016/j.compeleceng.2018.01.001

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The Performance of any VLSI circuit depends on its design architecture, which optimizes power and provides high reliability. To design any circuit with low power, power optimization of circuit at different levels is needed. Most of the system level architectures consists of sequential circuits, design of these circuits plays an pivotal role in reducing overall power of the system. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. In this brief, we propose a power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different Flip-flops and offers high reliability. The proposed counter design is evaluated and analyzed in terms of power in a standard 45 nm CMOS technology in CADENCE and also evaluated in Synopsys Design Compiler and IC Compiler for ASIC (Application Specific Integrated Circuit) synthesis results. The proposed counter design has lower power requirement and power-area product than existing counter architectures and the power reduction is more significant for widebit counters. (C) 2018 Elsevier Ltd. All rights reserved.

Keyword:

Counter

Up-down counter

Power consumption

Clock-power

Area

Power-area product

Power efficient synchronous counter design

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