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PowerSynth: A Power Module Layout Generation Tool

delete2019-06-01
delete54
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OA
AI
T
Tristan M. Evans *
Q
Quang Trung Le
S
Shilpi Mukherjee
I
Imam Al Razi
T
Tom Vrotsos
彭亚锐 封面图
彭亚锐 (Yarui Peng)
H
H. Alan Mantooth
DOI:10.1109/TPEL.2018.2870346delete
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摘要

摘要

En 中文
PowerSynth is a multiobjective optimization tool for rapid design and verification of power semiconductor modules. By using reduced order models for the calculation of electrical parasitics of the layout and thermal coupling between devices, optimal trace layout and die placement can be simultaneously achieved orders of magnitude faster than conventional finite element analysis (FEA) techniques. An overview of the tool, its modeling methods, model validation, and module layout optimization are presented. The electrical and thermal models are validated against FEA simulations and physical measurements of built modules generated from the tool. The FEA comparisons are performed with FastHenry and ANSYS Icepak to evaluate electrical parasitics and thermal behavior, respectively. A sample hardware prototype based on a half-bridge circuit topology is chosen for testing. Excellent agreement between the FEA simulations, experimental measurements, and PowerSynth predictions are demonstrated. Additionally, when compared with conventional simulation runtime and workflow, PowerSynth takes considerably less computation and user time to produce several candidate layout solutions from which a designer may easily balance selected tradeoffs.
Keyword:
Design automation
layout
optimization methods
power electronics
semiconductor device packaging
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期刊

IEEE Transactions on Power Electronics 封面图
IEEE Transactions on Power Electronics
IF:
6.5
论文数:
1.7W
被引数:
8.3W

机构

U
University of Arkansas System
学者数:
1.9W
论文数: 1.5W
被引数: 295
U
university of arkansas fayetteville
学者数:
5.2K
论文数: 4.5K
被引数: 2
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