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Processing architectures for smart pixel systems

delete1996-04-01
delete21
PRE
AI
D
D.S. Wills *
B
Baker, JM
C
Cat, HH
C
Chai, SM
C
Codrescu, L
C
CruzRivera, J
E
Eble, JC
G
Gentile, A
H
Hopper, MA
L
Lacy, WS
L
LopezLagunas, A
M
May, P
S
Smith, S
T
Taha, T
DOI：10.1109/2944.541872delete
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摘要

摘要

En 中文
Smart pixel architectures offer important new opportunities Tor low-cost, portable image processing systems, They provide greater I/O bandwidth and computing performance than systems based on CCD and microprocessors, However, finding a balance between performance, flexibility, efficiency, and cost depends on an evaluation of target applications, This paper describes several promising architectural approaches for the realization of videoputer systems and outlines example implementations being pursued at the Georgia Institute of Technology.
Keyword:
MASSIVELY PARALLEL PROCESSOR
SILICON CIRCUITRY
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期刊

I
IEEE Journal of Selected Topics in Quantum Electronics
IF:
5.1
论文数:
5.6K
被引数:
1.2W

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