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In this paper, we present an efficient approach to HW/SW partitioning of applications targeted for embedded soft-core SoPC and programmable logic. The methodology is based on the iterative performance analysis of the initial functional SW description and performance estimation of various HW/SW partitioning configurations. The main focus is on adequate profiling of arbitrary SW code regions (function or single instruction level) with clock-cycle accuracy without introducing additional execution overhead. In order to support the profiling for partitioning, we have developed the COMET Profiler tool. The performance analysis and estimation in the simulation and implementation domains are supported, necessitating no design and implementation of HW co-processing blocks for the partitioning evaluation. The design process is illustrated with two case studies. (c) 2004 Elsevier B.V. All rights reserved.
Keyword:
hardwarelsoftware co-design
HW/SW partitioning
field programmable gate array
embedded soft-core processor
performance analysis
profiling
system-on-programmable-chip (SoPC)
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