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Programmable interleaver design for analog iterative decoders
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DOI：10.1109/TCSII.2002.805022.png)
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Several programmable analog interleaver architectures for iterative decoders are proposed. The architectures are evaluated in terms of transistor count, path resistance, path capacitance, and programming logic. Interleavers built out of networks consisting of three layers of small crossbars are often deemed the best, reducing both switch count and capacitance by over 70% for an interleaver size of 100, as opposed to full crossbars, while maintaining full programmability.
Keyword:
analog decoders
error control codes
interleavers
iterative decoders
turbo codes
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