Realization model for brain computing

doi:10.1016/S0096-3003(99)00162-9

Realization model for brain computing

2000-05-01

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DOI：10.1016/S0096-3003(99)00162-9

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This paper reports on a newly developed micro-processor for brain-way computing. Brain-way means the method for acquiring function automatically as brain dose. The new device is designed to improve the performance of calculating a large number of connections and their self-organizing ability. Its instruction set is quite efficient to describe complex neurons and large-scale neural networks. A minimum processor system was constructed with a 35 K gate custom LSI (gate array) and four 1M-bit SRAMs, which can simulate over 1000 neurons and one million connections with real-time execution of calculation and learning. The chip includes a circuit to build a network linking each other, which can connect over 200 chips without any additional circuitry and can obtain about one million cells and 200 million connections. The flexible learning circuitry supports a few auto-assembly algorithms and in-forced algorithms such as back-propagation algorithms. Learning calculations execute complete back-ground processing by special circuitry. This paper describes the main features of the processor and the concept of brain computing which will be implemented by hardware logic fashion. (C) 2000 Published by Elsevier Science Inc. All rights reserved.

Realization model for brain computing

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