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Rei: A Reconfigurable Interconnection Unit for Array-Based CNN Accelerators
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DOI：10.1109/TETC.2023.3290138.png)
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摘要
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Convolutional Neural Network (CNN) is used in many real-world applications due to its high accuracy. The rapid growth of modern applications based on learning algorithms has increased the importance of efficient implementation of CNNs. The array-type architecture is a well-known platform for the efficient implementation of CNN models, which takes advantage of parallel computation and data reuse. However, accelerators suffer from restricted hardware resources, whereas CNNs involve considerable communication and computation load. Furthermore, since accelerators execute CNN layer by layer, different shapes and sizes of layers lead to suboptimal resource utilization. This problem prevents the accelerator from reaching maximum performance. The increasing scale and complexity of deep learning applications exacerbate this problem. Therefore, the performance of CNN models depends on the hardware's ability to adapt to different shapes of different layers to increase resource utilization. This work proposes a reconfigurable accelerator that can efficiently execute a wide range of CNNs. The proposed flexible and low-cost reconfigurable interconnect units allow the array to perform CNN faster than fixed-size implementations (by 45.9% for ResNet-18 compared to the baseline). The proposed architecture also reduces the on-chip memory access rate by 36.5% without compromising accuracy.
Keyword:
Adaptable architectures
array and vector processors
image processing and computer vision
parallel processors
reconfigurable hardware
special-purpose and application-based systems
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5.4
论文数:
1.1K
被引数:
3.4K
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