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Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey
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DOI：10.1016/j.sysarc.2026.103874.png)
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Abstract
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Reinforcement learning (RL) has emerged as a powerful paradigm for enabling adaptive, autonomous, and self-optimizing behavior in modern computing systems, particularly as applications increasingly migrate toward embedded, edge, and heterogeneous hardware platforms. Field-programmable gate arrays (FPGAs) and integrated circuits (ICs) offer compelling advantages for RL deployment, including low latency, energy efficiency, and fine-grained architectural customization, but they also introduce unique design challenges that differ substantially from conventional CPU- and GPU- based implementations. This review presents a comprehensive survey of RL implementations on FPGA and IC platforms, with a particular emphasis on architectural design, performance measurement, and hardware–algorithm co-design. A broad body of more than one hundred studies is systematically analyzed and organized into major RL families, ranging from model-based Markov decision processes and classical value-based methods to deep RL, Actor-critic (AC), policy-gradient (PG), and multi-agent approaches. The review further categorizes existing works according to abstraction levels, hardware realization strategies, and application domains, highlighting how different RL algorithms map onto reconfigurable and fixed hardware substrates. In contrast to prior surveys that focus narrowly on specific algorithms or platforms, this work provides a unified perspective spanning both FPGA and IC implementations, encompassing acceleration techniques, reconfigurable hardware approaches, energy-aware control, and system-level optimization. Detailed comparisons are provided in terms of resource utilization, latency, throughput, power consumption, and achieved performance gains. Additionally, this review identifies recurring architectural patterns, discusses practical limitations, and outlines open research challenges and future directions for RL-driven intelligent hardware systems. By consolidating design insights, evaluation metrics, and application trends, this review aims to serve as a comprehensive reference for researchers and practitioners working at the intersection of RL and hardware platforms.
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