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Reliability-Driven System-Level Synthesis for Mixed-Critical Embedded Systems
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DOI：10.1109/TC.2012.226.png)
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摘要
En 中文
This paper proposes a design methodology that enhances the classical system-level design flow for embedded systems to introduce reliability-awareness. The mapping and scheduling step is extended to support the application of hardening techniques to fulfill the required fault management properties that the final system must exhibit; moreover, the methodology allows the designer to specify that only some parts of the systems need to be hardened against faults. The reference architecture is a complex distributed one, constituted by resources with different characteristics in terms of performance and available fault detection/tolerance mechanisms. The approach is evaluated and compared against the most recent and relevant work, with an in-depth analysis on a large set of benchmarks.
Keyword:
Reliability
soft errors
system-level synthesis
design space exploration
mapping and scheduling
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