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Restructuring a software based MPEG-4 video decoder for short latency hardware acceleration
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DOI：10.1117/12.702333.png)
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Abstract
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The multimedia capabilities of emerging high-end battery powered mobile devices rely on monolithic hardware accelerators with long latencies to minimize interrupt and software overheads. When compared to pure software implementations, monolithic hardware accelerator solutions need an order of magnitude less power. However, they are rather inflexible and difficult to modify to provide support for multiple coding standards. A more flexible alternative is to employ finer grained short latency accelerators that implement the individual coding functions. Unfortunately, with this approach the software overheads can become very high, if interrupts are used for synchronizing the software and hardware. Preferably, the cost of hardware accelerator interfacing should be at the same level with software functions. In this paper we study the benefits attainable from such an approach. As a case study we restructure a MPEG-4 video decoder in a manner that enables the simultaneous decoding of multiple bit streams using short latency hardware accelerators. The approach takes multiple video bit streams as input and produces a multiplexed stream that is used to control the hardware accelerators without interrupts. The decoding processes of each stream can be considered as threads that share the same hardware resources. Software simulations predict that the energy efficiency of the approach would be significantly better than for a pure software implementation.
Keywords:
hardware accelerator
video decoding
MPEG-4
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