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Scaling silicon-based quantum computing using CMOS technology
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DOI：10.1038/s41928-021-00681-y.png)
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As quantum processors grow in complexity, attention is moving to the scaling prospects of the entire quantum computing system, including the classical support hardware. Recent results in high-fidelity control of individual spins in silicon, combined with demonstrations that these qubits can be manufactured in a similar fashion to field-effect transistors, create an opportunity to leverage the know-how of the complementary metal-oxide-semiconductor (CMOS) industry to address the scaling challenge at a system level. Here we review the prospects of scaling silicon-based quantum computing using CMOS technology. We consider the concept of a quantum computing system, which we decompose into three distinct layers-the quantum layer, the quantum-classical interface and the classical layer-and explore the challenges involved in their development, as well their assembly into an architecture. Silicon offers the enticing possibility that all layers can, in principle, be manufactured using CMOS technology, creating an opportunity to move from distributed quantum-classical systems to integrated quantum computing solutions. This Review examines the scaling prospects of quantum computing systems based on silicon spin technology and how the different layers of such a computer could benefit from using complementary metal-oxide-semiconductor (CMOS) technology.
Keyword:
SINGLE-SHOT READOUT
ELECTRON-SPIN
NANOMETER CMOS
QUBIT
GATE
DOT
OPERATION
CIRCUITS
MANIPULATION
INFORMATION
期刊
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40.9
论文数:
1.7K
被引数:
2.1W
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