Scope-aware data cache analysis for OpenMP programs on multi-core processors

doi:10.1016/j.sysarc.2019.04.001

2019-09-01

PRE

DOI：10.1016/j.sysarc.2019.04.001

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摘要

En 中文

OpenMP is the de facto standard parallel programming framework on shared memory architectures, which is not only widely used in general and high-performance computing but also draws increasing interests for real-time embedded systems. Choosing the appropriate assignment of loop iterations to threads is one of the most critical decisions when parallelizing loops, especially considering the large impact by caches behaviors to the program execution time. In this paper, we study data cache analysis for OpenMP programs with parallel loops. We first present a method considering the impact of the schedule clause in OpenMP programs on cache behavior. We capture the dynamic behavior of memory access by computing its temporal scope (the loop iterations where a given memory block is accessed for a given data reference) during address analysis. Based on the ACS representation, we present a temporal scope aware data cache miss calculation technique. Through the experimental result, we propose a convenient way to choose an appropriate parallelization scheme for OpenMP programs.

Keyword:

OpenMP

Multicores

Parallelism computing

Cache analysis