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Selector-only memory in Si-doped GeSeTe chalcogenide with superior endurance and memory window
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DOI：10.1039/d6tc00505e.png)
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Abstract
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Selector-only memory (SOM) devices based on chalcogenide materials are attractive candidates for high-density memory arrays. SOMs operate through polarity-dependent threshold switching and can retain distinct threshold voltage states Vth even after bias removal, thereby enabling simultaneous memory and selection functionality within crossbar architectures. This operation demands both robust endurance and a wide memory window (MW); however, current chalcogenide SOMs typically suffer from limited endurance and a narrow MW, which severely restrict their potential for multi-bit or high-density operations. We address these limitations by incorporating silicon (Si) into a W/GeSeTe/W structure. The optimized Si-doped device exhibits endurance exceeding 108 cycles and a significantly widened MW of 2.4 V, compared with 105 cycles and 0.7 V for the undoped GeSeTe device, while maintaining a low leakage current (3.2-11.5 nA). Mechanistic analysis reveals that Si incorporation induces two complementary effects: (1) the formation of stronger Si-Ge and Si-Se bonds that reinforce the amorphous network structure, and (2) an increase in trap depth difference (Delta Phi t) between the two switching states (0.021 -> 0.149 eV). This increase in Delta Phi t, attributed to the electronegativity difference between Si and its bonding partners (Ge, Se), directly accounts for the significant MW widening. Furthermore, Si incorporation suppresses defect migration and stabilizes the trap-energy landscape under prolonged cycling, resulting in consistent switching characteristics, enhanced thermal stability, and markedly improved reliability. Overall, Si doping simultaneously enhances the structural, electronic, and thermal robustness of GeSeTe, providing a practical and scalable route toward high-endurance, wide-window, and thermally stable SOM devices suitable for next-generation three-dimensional (3D) crossbar memory integration.
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