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Self-aware power management for multi-core microprocessors
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DOI：10.1016/j.suscom.2020.100480.png)
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Power management is one of the significant challenges to be addressed in multi-/many-core microprocessors. Furthermore, the multi-core microprocessors experience unforeseen scenarios such as performance degradation over time, manufacturing defects, power, and thermal impacts with time. Traditional power management techniques, though efficient, is not designed to handle such unseen scenarios. Furthermore, the variation in performance requirements is one of the challenges faced in the era of machine learning. We propose a self-aware power management scheme for multi-core microprocessors in this work to address the above-mentioned issues. We perform application-level power management in this work to overcome the overheads imposed by core-level power management and system-level power management inefficiency. The power management unit employs a linear predictor for workload prediction to perform DVFS. On top of the power manager, the self-aware controller is hierarchically placed to monitor the system components? health and adapt the power manager?s decision to meet the performance requirements and handle changes in system components? health. We evaluate the proposed self-aware power manager under externally provided high performance goals, and resource contention. A power saving of up to 16% compared to existing power management techniques, and 2.4? speedup with 25% additional power to satisfy high performance compared to power management without self-awareness for a microprocessor with up to 32-cores is achieved.
Keyword:
Self-awareness
Power management
Dynamic voltage and frequency scaling
Multi-core microprocessors
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